تحقیق به زبان انگلیسی: A Study on Self-Timed Adder

صبری: ۰۹۳۶۷۲۹۲۲۷۶

تحقیق به زبان انگلیسی: A Study on Self-Timed Adders عنوان تحقیق به زبان انگلیسی: azsoftir@gmail.com 0936-729-2276 azsoft.ir azsoftir@gmail.com 0936-729-2276 azsoft.ir A Study on Self-Timed Adders شامل یک تحقیق جامع به زبان انگلیسی و با کمک نرم افزار latex به فرمت مقاله در اورده شده. که خلاصه ی جامعی از مقالات مرجع میباشد [1] A.J. Martin, “Compiling communicating processes into delay-insensitive VLSI circuits,” Distributed Computing, vol. 1, no. 4, pp. 226-234, December 1986. [2] A.J. Martin, “The limitation to delay-insensitivity in asynchronous circuits,” Proc. 6th MIT Conf. on Advanced Research in VLSI, pp. 263-278, MIT Press, 1990. azsoftir@gmail.com 0936-729-2276 azsoft.ir azsoftir@gmail.com 0936-729-2276 azsoft.ir [3] E. Muller and W.S. Bartky, “A theory of asynchronous circuits,” Proc. International Symp. on the Theory of Switching, part I, pp. 204-243, Harvard University Press, 1959. [4] J. Sparso and S.B. Furber (Eds.), Principles of Asynchronous Circuit Design: A Systems Perspective, Kluwer Academic Publishers, 2001. [5] C.L Seitz, “System Timing,” in Introduction to VLSI Systems, C. Mead and L. Conway (Eds.), pp. 218-262, Addison-Wesley, Reading, MA, 1980. [6] J.L. Hennessy and D.A. Patterson, Computer Architecture: A Quantitative Approach. Morgan Kaufmann, 1990. [7] M.A. Franklin and T. Pan, “Performance Comparison of Asynchronous Adders,” Proc. Int’l Symp. Advanced Research in Asynchronous Circuits and Systems, pp. 117-125, Nov. 1994. azsoftir@gmail.com 0936-729-2276 azsoft.ir azsoftir@gmail.com 0936-729-2276 azsoft.ir [8] J.D. Garside, “A CMOS VLSI Implementation of an Asynchronous ALU,” Asynchronous Design Methodologies, S. Furber and M. Edwards, eds., vol. A-28 of IFIP Trans., pp. 181-207 1993. [9] A. Kondratyev, M. Kishinevsky, B. Lin, P. Vanbekbergen and A. Yakovlev, “Basic gate implementation of speedindependent circuits,” Proc. 31st ACM/IEEE Design Automation Conference, pp. 56-62, 1994. [10] P.A. Beerel and T.H.-Y. Meng,“Automatic gate-level synthesis of speed-independent circuits,” Proc. IEEE/ACM International Conf. on Computer-Aided Design, pp. 581- 586, 1992. [11] J. Cortadella, M. Kishinevsky, A. Kondratyev, L. Lavagno and A. Yakovlev, Logic Synthesis of Asynchronous Controllers and Interfaces, Springer-Verlag Publishing, 2002. [12] B. Folco, V. Bregier, L. Fesquet and M. Renaudin, Technology mapping for area optimized quasi delay insensitive circuits, Proc. International Conf. on Very Large Scale Integration, pp. 146-151, 2005. [13] J. Sparso and J. Staunstrup, “Delay-insensitive multi-ring structures,” Integration, the VLSI journal, vol. 15, no. 1, pp. 313-340, Oct. 1993. [14] P. Balasubramanian and D.A. Edwards, “A delay efficient robust self-timed full adder,” Proc. 3rd IEEE International azsoftir@gmail.com 0936-729-2276 azsoft.ir azsoftir@gmail.com 0936-729-2276 azsoft.ir Design and Test Workshop, pp. 129-134, 2008 سفارش پروژه موضوعات مرتبط: پروژه درسی، تحقیق به زبان انگلیسی برچسبها: A Study on Self, Timed Adders, تحقیق, تحقیق به زبان انگلیسی, latex منتشر شده در تاریخ جمعه دوازدهم اردیبهشت 1393 توسط ADMIN نظر دهید تحقیق به زبان انگلیسی: Square Root And Squaring Algorithms عنوان تحقیق به زبان انگلیسی: Square Root And Squaring Algorithms شامل یک تحقیق جامع به زبان انگلیسی و با کمک نرم افزار latex به فرمت مقاله در اورده شده. که خلاصه ی جامعی از مقالات مرجع میباشد [1] C. V. RAMAMOORTHY, J. R. GOODMAN, and K. H. KIM,“ Some properties of iterative square-rooting methods using high-speed multiplication, ” IEEE, vol. 21, Aug. 1972. [2] B. F.Dinechin, M.Joldes and G.Revy,“ Multiplicative square root algorithms for fpgas, IEEE, 2010. [3] D. Zuras,“ More on Squaring and Multiplying Large Integers,” IEEE Transactions on Computers, Vol. 43, No. 8, pp. 899-908, August 1994. [4] J. Guajardo and C. Paar,“ Modified Squaring Algorithm,” Available from http://www.crypto.ruhr-uni-bochum.de/guajard o/cv.htmlpubs. [5] B. Parhami, “Computer Arithmetic-Algorithms and Hardware” Oxford University Press, 2000. low-power full-adder cell with new technique in desining logical gate based on static مقاله شبیه سازی شده کد پروژه:1531 azsoftir@gmail.com 0936-729-2276 azsoft.ir azsoftir@gmail.com 0936-729-2276 azsoft.ir موضوع:گیت های منطقی Microelectronics شبیه سازی مقاله به کمک hspice و L-editهمراه با Word و پاورپوینت شامل:مقاله اصلی + فایل شبیه سازی با نرم افزارhspice +گزارش کامل از خلاصه ای از مقاله و نتایج شبیه سازی azsoftir@gmail.com 0936-729-2276 azsoft.ir azsoftir@gmail.com 0936-729-2276 azsoft.ir عنوان مقاله: A novel low-power full-adder cell with new technique in desining logical gate based on static cmos inverter سلول جمع کننده کم مصرف با تکنیکی جدید در طراحی گیت های منطقی Address: sciencedirect Abstract A new low-power full-adder based on CMOS inverter is presented. This full-adder is comprised of inverters. Universal gates such as NOR, NAND and MAJORITY-NOT gates are implemented with a set of inverters and non-conventional implementation of them. In the proposed design approach the time consuming XOR gates are eliminated. As full-adders are frequently employed in a tree-structured configuration for high-performance arithmetic circuits, a cascaded simulation structure is employed to evaluate the full-adders in a realistic application environment. The circuits being studied were optimized for energy efficiency using 0.18 μm and 90 nm CMOS process technologies. The proposed full-adder shows full swing logic, balanced outputs and strong output drivability. It is also observed that the presented design can be utilized in many cases especially whenever the lowest possible power consumption is targeted. Circuits layout implementations and checking their functionality have been done using Cadence IC package and Synopsys HSpice, respectively. Keywords Low-power Full-adder; Low-power CMOS design; Inverter-based full-adder design; Transmission gate azsoftir@gmail.com 0936-729-2276 azsoft.ir azsoftir@gmail.com 0936-729-2276 azsoft.ir